1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to the design of integrated circuits using predesigned and preverified core modules.
2. Description of the Related Art
In the past, integrated circuits were typically designed by defining the functionality of the integrated circuit as a whole and then designing from scratch the circuitry to implement the functionality. Computer aided design tools have long been employed to assist in the design of the transistor level circuitry. Upon definition of the transistor level circuitry, the mask layout of the integrated circuit is created.
Integrated circuits were often limited as to the number of transistors which could be employed therein. Accordingly, the amount of functionality included in a particular integrated circuit was rather limited. Therefore, it was relatively efficient to design each new integrated circuit individually from scratch, without directly leveraging off of the chip design of past work.
More recently, the number of transistors which are included upon a given integrated circuit has increased dramatically. Integrated circuits have thereby become more complex, integrating larger amounts of functionality as the number of transistors has grown. Since integrated circuits are increasing in complexity, the amount of time required to develop and fully test the new integrated circuit is increasing as well. At the same time, due to the pace of change in the semiconductor industry, the time-to-market for a product is required to be shorter.
Accordingly, it has become increasingly popular to design integrated circuits by selecting predesigned and preverified core modules for inclusion within the integrated circuit. Each core module performs a designated sub-function and is selected from a "library" of predefined and preverified core modules. The core modules can be used in conjunction with other core modules or custom logic to perform the overall functionality of the integrated circuit. Since each core module is predefined and preverified, the designer of the integrated circuit need not be concerned with the details of implementing the sub-function implemented by the core module. Instead, the designer includes the core module in the integrated circuit design and designs additional sub-functions for which a core is not available in custom logic. Time-to-market for the integrated circuit may thereby be decreased in comparison to the amount of time formerly required to design the functionality of the integrated circuit as a whole.
Although integrated circuit design techniques employing predefined core modules have been largely successful in accommodating expedient time-to-market, certain problems have emerged which hinder the expediency of the design, particularly in high-frequency applications. One such problem relates to minimizing clock skew between the predefined core modules and the custom logic. That is, while each of the predefined core modules are typically designed with internal clock distribution networks that are balanced, clock skew between various core modules and the custom logic may become problematic, particularly in high frequency applications. This problem occurs in part since the loading associated with the clock input of each core module may differ drastically among the core modules and may differ drastically from the loading presented by the clock input of the custom logic. Typically, substantial time and effort must be devoted to reducing clock skew between the core modules and the custom logic, and often extra logic such as phase locked loop circuits or data lock up latches must be employed. Accordingly, the integrated circuit may become larger in size, may become more difficult to test, and may be more complex to design. A method is desirable wherein an integrated circuit may be designed using predefined core modules integrated with custom logic wherein clock skew may be reduced without the requirement of additional phase lock loop circuits or lock up latches, and wherein overall design and test may be simplified.